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• zebra_hun veterán

  #13435 2024-04-11 13:57:04

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  zebra_hun

  veterán

  BCLK Frequency : DRAM Frequency Ratio [100:100]
  Memory Controller : DRAM Frequency Ratio [1:2]
  DRAM Frequency [DDR5-7600MHz]
  
  Maximus Tweak [Mode 2]
  DRAM CAS# Latency [34]
  DRAM RAS# to CAS# Delay Read [44]
  DRAM RAS# to CAS# Delay Write [44]
  DRAM RAS# PRE Time [44]
  DRAM RAS# ACT Time [56]
  DRAM Command Rate [2N]
  DRAM RAS# to RAS# Delay L [12]
  DRAM RAS# to RAS# Delay S [8]
  DRAM REF Cycle Time 2 [480]
  DRAM REF Cycle Time Same Bank [Auto]
  DRAM Refresh Interval [131071]
  DRAM WRITE Recovery Time [Auto]
  DRAM READ to PRE Time [12]
  DRAM FOUR ACT WIN Time [32]
  DRAM WRITE to READ Delay L [24]
  DRAM WRITE to READ Delay S [8]
  DRAM CKE Minimum Pulse Width [19]
  DRAM Write Latency [32]
  Ctl0 dqvrefup [162]
  Ctl0 dqvrefdn [80]
  
  Vddq Training [Disabled]

  tRDRD_sg_Training [Auto]
  tRDRD_sg_Runtime [16]
  tRDRD_dg_Training [Auto]
  tRDRD_dg_Runtime [8]
  tRDWR_sg [20]
  tRDWR_dg [20]
  tWRWR_sg [16]
  tWRWR_dg [8]
  tWRRD_sg [Auto]
  tWRRD_dg [Auto]
  tRDRD_dr [0]
  tRDRD_dd [Auto]
  tRDWR_dr [0]
  tRDWR_dd [Auto]
  tWRWR_dr [0]
  tWRWR_dd [Auto]
  tWRRD_dr [0]
  tWRRD_dd [Auto]
  tRPRE [Auto]
  tWPRE [Auto]
  tWPOST [Auto]
  tWRPRE [64]
  tPRPDEN [2]
  tRDPDEN [43]
  tWRPDEN [65]
  tCPDED [19]
  tREFIX9 [Auto]
  Ref Interval [Auto]
  tXPDLL [Auto]
  tXP [29]
  tPPD [2]
  
  tXSDLL [2559]
  
  tXSR [645]
  
  MRC Fast Boot [Disabled]
  

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